1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a word-line driver for activating a word-line corresponding to a row address which is supplied from an external system out of the semiconductor memory device.
2. Description of the Prior Art
It has been well known that high packing density in a semiconductor memory device must accompany with achievements of high data accessing speed and low power dissipation. Though to implement the demands against the high density semiconductor memory device meets some limitations relevant to technical faculties for designing and manufacturing an integrated circuit at present, various efforts to be near the achievements as possible are being conducted.
In grading up the speed rate of the data access operation, that is to be advanced with the high packing density of the semiconductor memory device, the speed for selecting a memory cell as well as for sensing data on a pair of bit lines should be faster. To increase the speed for selecting a memory cell, a word-line connected to the memory cell must be activated in response to a row address which is input into the semiconductor memory device. As well known in this art, a semiconductor memory device, in order to select a word-line, essentially has an address input buffer for receiving an external row address, a word-line decoder (or a row decoder) for converting an internal row address from the address buffer into a word-line decoding signal (or row decoding signal) and a word-line driver for activating a word-line corresponding with the word-line decoding signal generated from the word-line decoder. The word-line driver has been developed in point of improving the reliability and operating speed, while the number of the word line drivers employed in the semiconductor memory device has been increased in accordance with the number of the memory cells.
With respect to techniques for the word-line driver, U.S. Pat. No. 4,514,829, issued on Apr. 30, 1985 to Hu H. Chao, provides a word-line driver for directing high packing density, high data accessing speed and low power dissipation. FIG. 1 shows the circuit configuration of Chao's word-line driver. In FIG. 1, two word-line drivers are selectively activated in response to the word-line decoding signal ADS generated from a word-line decoder (not shown). For the selective activation with the pair of word-line drivers, a row selecting signal which, as a source power, is applied to one word-line driver makes an influence to the other word-line driver. The circuit elements of M1, M2 and M3 form a first word-line driver, and those of M4, M5 and M6 make a second word-line driver. The signal R1 and 112 are the row selecting signals used as source powers respectively for the word-lines WL0 and WL1.
Concerning the operation for activating the word-line driver, the first and second word-line drivers are not activated when the word-line decoding signal ADS has been applied thereto as a high logic state (hereinbelow referred to a voltage level the same or near to an internal power supply voltage). On the contrary, receipt with the word-line decoding signal ADS of a low logic state (hereinbelow referred to a voltage level the same or near to ground voltage) makes the word-line drivers active. PMOS (P-channel Metal-Oxide-Semiconductor) transistor M1 of the first word-line driver and PMOS transistor M4 of the second word-line driver are turned on in response to the word-line decoding signal ADS of the low logic state. Assuming that the current row address is to select the word line WL0, the row selecting signal R1 will be active. On the other hand, assuming that the current row address is for selecting the word line WL1, the row selecting signal R2 will be active. Thus, when the word line WL0 is selected by the current row address the row selecting signals R1 and R2 become high and low logic states, respectively. Then, the word line WL0 has the same voltage level as that of the row selecting signal R1, and the word line WLI retains the ground voltage level by the turning-on of NMOS transistors M5 and M6. When the current row address selects the word line WL1 the row selecting signals R1 and R2 become respectively low and high logic states, which makes the word line WL1 retain the same voltage with that of the row selecting signal 112 while the word line WL0 retains the ground voltage level.
The word-line driver as shown in FIG. 1, however, is highly disadvantageous to an advanced semiconductor memory device with a larger capacity than 64 mega-bits, due to its own architecture consisting of at least six transistors which are necessary to drive two word lines. The occupation by the six transistors for two word lines causes the area for a peripheral circuit including a plurality of the word-line drivers to be increased, thus losing the use of valuable chip area and resulting in higher power dissipation rate.
U.S. Pat. No. 4,953, 133 describes another conventional configuration for the word-line driver, as shown in FIG. 2, in which, though six transistors are employed therein, one row selecting signal is utilized for one word-line driver so as to reduce unnecessary power dissipation. When a word-line decoding signal ADS is on high logic state a PMOS transistor M7 is turned off and a NMOS transistor M8 is turned on so that word lines WL0 and WL1 both retain voltage levels of low logic states if at least one of the row selecting signals R1 and R2 is on high logic state. The transistors M7 and M8 are turned on and off, respectively when the word-line decoding signal ADS is applied thereto as low logic state. In FIG. 2, assuming that a word-line driver for selecting a word line WL1 consists of transistors M9 and M10 and that a word-line driver for selecting a word line WL0 consists of transistors M11 and M12, the word-line driver receiving one of the row selecting signals R1 or 112 that is on low logic state, will activate and output a corresponding one of the word lines WL0 or WL1 at the high state. Also in the conventional word-line driver of FIG. 2, two word lines need six transistors as in the circuit of FIG. 1, which results in the increase of chip area occupied by a peripheral circuit including a plurality of such word-line drivers.